Commit 8351a160 authored by David Trudgian's avatar David Trudgian

Fix R intel module name in yml

parent e30cbd75
......@@ -107,7 +107,7 @@ workflow_parameters:
# The workflow must publish all final output into $baseDir
# Name of the R module that the vizapp will run against
vizapp_r_module: 'R/3.2.1-Intel'
vizapp_r_module: 'R/3.2.1-intel'
# List of any CRAN packages, not provided by the modules, that must be made
# available to the vizapp
......@@ -118,4 +118,4 @@ vizapp_cran_packages:
# # List of any Bioconductor packages, not provided by the modules, that must be made
# available to the vizapp
vizapp_bioc_packages:
- chipseq
\ No newline at end of file
- chipseq
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